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| 1. general description the UJA1164 is a mini high-speed can sy stem basis chip (sbc) containing an iso 11898-2/5 compliant hs-can transceiver and an integrated 5 v/100 ma supply for a microcontroller. it also features a watchdog and a serial peripheral interface (spi). the UJA1164 can be operated in a very low-current standby mode with bus wake-up capability and supports iso 11898-6 compliant autonomous can biasing. a number of configuration sett ings are stored in non-volatile memory, allowing the sbc to be adapted for use in a specific application. this makes it possib le to configure the power-on behavior of the UJA1164 to meet the requirements of different applications. 2. features and benefits 2.1 general ? iso 11898-2 and iso 11898-5 compliant high-speed can transceiver ? autonomous bus biasing according to iso 11898-6 ? fully integrated 5 v/100 ma low-drop voltage regulator for 5 v microcontroller supply (v1) ? bus connections are truly floating when power to pin bat is off 2.2 designed for automotive applications ? ? 8 kv electrostatic discharge (esd) protection, according to the human body model (hbm) on the can bus pins ? ? 6 kv esd protection, according to iec 61000-4-2 on the can bus pins and on pin bat ? can bus pins short-circuit proof to ? 58 v ? battery and can bus pins protected against automotive transients according to iso 7637-3 ? very low quiescent curr ent in standby mode wit h full wake-up capability ? leadless hvson14 package (3.0 mm ? 4.5 mm) with improved automated optical inspection (aoi) capability and low thermal resistance ? dark green product (halogen free and rest riction of hazardous substances (rohs) compliant) 2.3 low-drop voltage regulator for 5 v microcontroller supply (v1) ? 5 v nominal output; ? 2 % accuracy ? 100 ma output cu rrent capability UJA1164 mini high-speed can system ba sis chip with standby mode & watchdog rev. 1 ? 5 august 2013 product data sheet
UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 2 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog ? current limiting above 150 ma ? on-resistance of 5 ? (max) ? support for microcontroller ram retention down to a battery voltage of 2 v ? undervoltage reset with selectable detection thresholds: 60 %, 70 %, 80 % or 90 % of output voltage ? excellent transient response with a 4.7 ? f ceramic output capacitor ? short-circuit to gnd/overload protection on pin v1 2.4 power management ? standby mode featuring very low supply current; voltage v1 remains active to maintain the supply to the microcontroller ? remote wake-up capability via standard can wake-up pattern ? wake-up source recognition ? remote wake-up can be disabled to reduce current consumption 2.5 system control and diagnostic features ? mode control via the serial peripheral interface (spi) ? overtemperature warning and shutdown ? watchdog with independent clock source ? watchdog can be operated in window, timeout and autonomous modes ? optional cyclic wake-up in watchdog timeout mode ? watchdog automatically re-enabled when wake-up event captured ? watchdog period selectable between 8 ms and 4 s ? supports remote flash programming via the can bus ? 16-, 24- and 32-bit spi for conf iguration, control and diagnosis ? bidirectional reset pin with variable power- on reset length to support a variety of microcontrollers ? configuration of selected functions via non-volatile memory 3. ordering information table 1. ordering information type number package name description version UJA1164tk hvson14 plastic thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 ? 4.5 ? 0.85 mm sot1086-2 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 3 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 4. block diagram fig 1. block diagram of UJA1164 UJA1164 5 v microcontroller supply (v1) rstn v1 watchdog hs-can canh canl txd rxd sdi sck scsn sdo spi 015aaa268 5 3 13 12 bat 10 4 1 8 11 6 14 gnd 2 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 4 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 5. pinning information 5.1 pinning 5.2 pin description [1] hvson14 package die supply grou nd is connected to both the gnd pi n and the exposed center pad. the gnd pin must be soldered to board ground. for enhanc ed thermal and electrical performance, it is recommended to also solder the exposed center pad to board ground. fig 2. pin configuration diagram terminal 1 index area 015aaa441 UJA1164 txd 1 gnd 2 3 rxd 4 5 sdo 6 i.c. scsn canh canl sdi bat i.c. sck 7 14 13 12 11 10 9 8 transparent top view v1 rstn table 2. pin description symbol pin description txd 1 transmit data input gnd 2 [1] ground v1 3 5 v microcontroller supply voltage rxd 4 receive data output; reads out data from the bus lines rstn 5 reset input/output sdo 6 spi data output i.c. 7 internally connected; should be left floating or connected to gnd sck 8 spi clock input i.c. 9 internally connected; should be left floating or connected to gnd bat 10 battery supply voltage sdi 11 spi data input canl 12 low-level can bus line canh 13 high-level can bus line scsn 14 spi chip select input UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 5 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6. functional description 6.1 system controller the system controller manages register confi guration and controls the internal functions of the UJA1164. detailed device status information is collected and made available to the microcontroller. 6.1.1 operating modes the system controller contains a state machine that supports six operating modes: normal, standby, reset, forced normal, overtemp and off. the state transitions are illustrated in figure 3 . 6.1.1.1 normal mode normal mode is the active operating mode. in this mode, all the hardware on the device is available and can be activated (see ta b l e 3 ). voltage regulator v1 is enabled to supply the microcontroller. the can interface can be configured to be active and thus to support normal can communication. depending on the spi register settings, the watchdog may be running in window or timeout mode. normal mode can be selected from standby mode via an spi command (mc = 111). 6.1.1.2 standby mode standby mode is the UJA1164?s power saving mode, offering reduced current consumption. the transceiver is unable to transmit or receive data in standby mode. the spi remains enabled and v1 is still active; the watchdog is active (in timeout mode) if enabled. if remote can wake-up is enabled (cwe = 1; see ta b l e 2 4 ), the receiver monitors bus activity for a wake-up request. the bus pins are biased to gnd (via r i(cm) ) when the bus is inactive for t > t to(silence) and at approximately 2.5 v when there is activity on the bus (autonomous biasing). pin rxd is forced low when any enabled wake-up event is detected. this can be either a regular wake-up (via the can bus) or a diagnostic wake-up such as an overtemperature event (see section 6.8 ). the UJA1164 switches to standby mode via reset mode: ? from off mode if the battery voltage rise s above the power-on detection threshold (v th(det)pon ) ? from overtemp mode if the chip temperature falls below the overtemperature protection release threshold, t th(rel)otp standby mode can also be selected from normal mode via an spi command (mc = 100). UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 6 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.1.1.3 reset mode reset mode is the reset execution state of the sbc. this mode ensures that pin rstn is pulled down for a defined time to allow the microcontroller to start up in a controlled manner. the transceiver is unable to transmit or rece ive data in reset mode. the spi is inactive; the watchdog is disabled; v1 and ov ertemperature detection are active. the UJA1164 switches to reset mode from any mode in response to a reset event (see ta b l e 5 for a list of reset sources). the UJA1164 exits reset mode: ? and switches to standby mode if pin rstn is released high ? and switches to forced normal mode if bit fnmc = 1 ? if the sbc is forced into off or overtemp mode if a v1 undervoltage event forced the transit ion to reset mo de, the UJA1164 will remain in reset mode until the voltage on pin v1 has recovered. fig 3. UJA1164 system controller state diagram standby mc = normal 015aaa271 mc = standby normal no overtemperature overtemp rstn = high overtemperature event from any mode except off reset power-on off from any mode v bat undervoltage v1 undervoltage any reset event forced normal from reset mode if fnmc = 1 any reset event mtp programming completed or mtp factory presets restored UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 7 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.1.1.4 off mode the UJA1164 switches to off mode when the ba ttery is first connected or from any mode when v bat < v th(det)poff . only power-on detection is enabled; all other modules are inactive. the UJA1164 starts to boot up when the battery voltage rises above the power-on detection threshold v th(det)pon (triggering an initializat ion process) and switches to reset mode after t startup . in off mode, the can pins disengage from the bus (zero load; high-ohmic). 6.1.1.5 overtemp mode overtemp mode is provided to prevent the UJA1164 being damaged by excessive temperatures. the UJA1164 switches immedi ately to overtemp mode from any mode (other than off mode) when the global chip temperature rises above the overtemperature protection activation threshold, t th(act)otp . to help prevent the loss of data due to over heating, the UJA1164 issues a warning when the ic temperature rises above the overtemperature warning threshold (t th(warn)otp ). when this happens, status bit otws is set and an overtemperature warning event is captured (otw = 1), if enabled (otwe = 1). in overtemp mode, the can transmitter and receiver are disabled and the can pins are in a high-ohmic state. no wake-up event will be detected, but a pending wake-up will still be signalled by a low level on pin rxd, which will persist after the overtemperature event has been cleared. v1 is off and pin rstn is driven low. the UJA1164 exits overtemp mode: ? and switches to reset mode if the chip temperature falls below the overtemperature protection release threshold, t th(rel)otp ? if the device is forced to switch to off mode (v bat < v th(det)poff ) 6.1.1.6 forced normal mode forced normal mode simplifies sbc testing and is useful for initial prototyping and failure detection, as well as first flashing of the mi crocontroller. the watchdog is disabled in forced normal mode. the low-drop voltage regulator (v1) and the can transceiver are active. bit fnmc is factory preset to 1, so the uja1 164 initially boots up in forced normal mode (see table 8 ). this allows a newly installed device to be run in normal mode without a watchdog. so the microcontroller can be flas hed via the can bus in the knowledge that a watchdog timer overflow will not trigger a system reset. the register containing bit fnmc (address 74 h) is stored in non-volatile memory (see section 6.9 ). so once bit fnmc is programmed to 0, the sbc will no longer boot up in forced normal mode, allowing the watchdog to be enabled. even in forced normal mode, a reset event (e.g. an external reset or a v1 undervoltage) will trigger a transition to reset mode with normal reset mode b ehavior (e.g. can goes offline). however, when the UJA1164 exits re set mode, it will return to forced normal mode instead of switching to standby mode. in forced normal mode, only the main status register, the watchdog status register, the identification register and registers stored in non-volatile memory can be read. the non-volatile memory area is fu lly accessible for writing as long as the UJA1164 is in the UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 8 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog factory preset state (for details see section 6.9 ). the UJA1164 switches from reset mode to forced normal mode if bit fnmc = 1. 6.1.1.7 hardware characterization for the UJA1164 operating modes [1] when the sbc switches from reset, standby or normal mode to of f mode, v1 behaves as a current source during power down while v bat is between 3 v and 2 v. [2] window mode is only active in normal mode. 6.1.2 system control registers the operating mode is selected via bits mc in the mode control register. the mode control register is accessed via spi address 0x01 (see section 6.13 ). the main status register can be accessed to monitor the status of the overtemperature warning flag and to determine whether the uj a1164 has entered normal mode after initial power-up. it also indicates the source of the most recent reset event. table 3. hardware characterization by functional block block operating mode off forced normal standby normal reset overtemp v1 off [1] on on on on off rstn low high high high low low spi disabled active active active disabled disabled watchdog off off determined by bits wmc (see ta b l e 7 ) [2] determined by bits wmc [2] off off can floating active offline active/ offline/ listen-only (determined by bits cmc; see table 14 ) offline floating rxd v1 level can bit stream v1 level/low if wake-up detected can bit stream if cmc = 01/10/11; otherwise same as standby v1 level/low if wake-up detected v1 level/low if wake-up detected table 4. mode control register (address 01h) bit symbol access value description 7:3 reserved r - 2:0 mc r/w mode control: 100 standby mode 111 normal mode table 5. main status register (address 03h) bit symbol access value description 7 reserved r - 6 otws r overtemperature warning status: 0 ic temperature below overtemperature warning threshold 1 ic temperature above overtemperature warning threshold UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 9 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.2 watchdog the UJA1164 contains a watchdog that supports three operating modes: window, timeout and autonomous. in window mode (available only in sbc normal mode), a watchdog trigger event within a closed watchdog window resets the watchdog timer. in timeout mode, the watchdog runs continuously and can be reset at any time within the timeout time by a watchdog trigger. watchdog timeout mode can also be used for cyclic wake-up of the microcontroller. in autonomous mode, the watchdog can be off or in timeout mode (see section 6.2.4 ). the watchdog mode is selected via bits wmc in the watchdog control register ( ta b l e 7 ). the sbc must be in standby mode when the watchdog mode is changed. if window mode is selected (wmc = 100), the watchdog will remain in (or switch to) timeout mode until the sbc enters normal mode. any atte mpt to change the watchdog operating mode (via wmc) while the sbc is in normal mode will cause the UJA1164 to switch to reset mode and the reset source status bits (r ss) will be set to 1000 0 (?illegal watchdog mode control access?; see ta b l e 5 ). eight watchdog periods are supported, from 8 ms to 4096 ms. the watchdog period is programmed via bits nwp. the selected period is valid for both window and timeout modes. the default watchdog period is 128 ms. a watchdog trigger event resets the watchdog timer. a watchdog trigger event is any valid write access to the watchdog control register. if the watchdog mode or the watchdog period have changed as a result of the write access, the new values are immediately valid. 5 nms r normal mode status: 0 UJA1164 has entered normal mode (after power-up) 1 UJA1164 has powered up but has not yet switched to normal mode 4:0 rss r reset source status: 00000 exited off mode (power-on) 01110 watchdog triggered too early (window mode) 01111 watchdog overflow (window mode or timeout mode with wdf = 1) 10000 illegal watchdog mode control access 10001 rstn pulled down externally 10010 exited overtemp mode 10011 v1 undervoltage table 5. main status register (address 03h) ?continued bit symbol access value description UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 10 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] default value if sdmc = 1 (see section 6.2.1 ) [2] default value. [3] selected in standby mode but only activated when the sbc switches to normal mode. the watchdog is a valuable safety mechanism, so it is critical th at it is configured correctly. two features are provided to prevent watchdog parameters being changed by mistake: ? redundant states of configuration bits wmc and nwp ? reconfiguration protection in normal mode redundant states associated with control bits wmc and nwp ensure that a single bit error cannot cause the watchdog to be configur ed incorrectly (at least two bits must be changed to reconfigure wmc or nwp). if an atte mpt is made to write an invalid code to wmc or nwp (e.g. 011 or 1001 respectively), the spi operation is abandoned and an spi failure event is captured, if enabled (see section 6.8 ). two operating modes have a major impact on the operation of the watchdog: forced normal mode and software development mode (software development mode is provided for test purposes and is not an sbc operating mode; the UJA1164 can be in any mode with software development mode enabled; see section 6.2.1 ). these modes are enabled and disabled via bits fnmc and sdmc resp ectively in the sbc configuration control table 6. summary of watchdog settings watchdog configuration via spi fnmc000 0 1 sdmcxx0 1 x wmc 100 (window) 010 (timeout) 001 (autonomous) 001 (autonomous) n.a. sbc operating mode normal mode window timeout timeout off off standby mode (rxd high) timeout timeout off off off standby mode (rxd low) timeout timeout timeout off off other modes off off off off off table 7. watchdog control register (address 00h) bit symbol access value description 7:5 wmc r/w watchdog mode control: 001 [1] autonomous mode 010 [2] timeout mode 100 [3] window mode 4 reserved r - 3:0 nwp r/w nominal watchdog period 1000 8 ms 0001 16 ms 0010 32 ms 1011 64 ms 0100 [2] 128 ms 1101 256 ms 1110 1024 ms 0111 4096 ms UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 11 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog register (see ta b l e 8 ). note that this register is loca ted in the non-volatile memory area (see section 6.8 ). in forced normal mode (fnm), th e watchdog is completely disabled. in software development mode (sdm), the watch dog can be disabled or activated for test purposes. information on the status of th e watchdog is available from the watchdog status register ( ta b l e 9 ). this register also indicates whether forced normal and so ftware development modes are active. [1] factory preset value. table 8. sbc configuration control register (address 74h) bit symbol access value description 7:6 reserved r - 5:4 v1rtsuc r/w v1 reset threshold (defined by bit v1rtc) at start-up: 00 [1] v1 undervoltage detection at 90 % of nominal value at start-up (v1rtc = 00) 01 v1 undervoltage detection at 80 % of nominal value at start-up (v1rtc = 01) 10 v1 undervoltage detection at 70 % of nominal value at start-up (v1rtc = 10) 11 v1 undervoltage detection at 60 % of nominal value at start-up (v1rtc = 11) 3 fnmc r/w forced normal mode control: 0 forced normal mode disabled 1 [1] forced normal mode enabled 2 sdmc r/w software development mode control: 0 [1] software development mode disabled 1 software development mode enabled 1:0 reserved r - table 9. watchdog status register (address 05h) bit symbol access value description 7:4 reserved r - 3 fnms r 0 sbc is not in forced normal mode 1 sbc is in forced normal mode 2 sdms r 0 sbc is not in software development mode 1 sbc is in software development mode 1:0 wds r watchdog status: 00 watchdog is off 01 watchdog is in first half of window 10 watchdog is in second half of window 11 reserved UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 12 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.2.1 software development mode software development mode is provided to simplify the software design process. when software development mode is enabled, the watchdog starts up in autonomous mode (wmc = 001) and is inactive after a system reset, overriding the default value (see ta b l e 7 ). the watchdog is always off in autono mous mode if softwa re development mode is enabled (sdmc = 1; see ta b l e 1 0 ). software can be run without a watchdog in so ftware development m ode. however, it is possible to activate and deacti vate the watchdog for test purposes by selecting window or timeout mode via bits wmc while the sbc is in standby mode (note that window mode will only be activated when the sbc switches to normal mode). so ftware development mode is activated via bits sdmc in non-volatile memory (see ta b l e 8 ). 6.2.2 watchdog behavior in window mode the watchdog runs continuously in window mode. the watchdog will be in window mode if wmc = 100 and the UJA1164 is in normal mode. in window mode, the watchdog can only be triggered during the second half of the watchdog period. if the watchdog overflows, or is triggered in the first half of the watchdog period (before t trig(wd)1 ), a watchdog failure event is captured (if enabled) and a system reset is performed. after the s ystem reset, the watchdog failu re event is indicated in the system event status register (wdf = 1; see table 19 ). if the watchdog is triggered in the second half of the watchdog period (after t trig(wd)1 but before t trig(wd)2 ), the watchdog timer is restarted. 6.2.3 watchdog behavior in timeout mode the watchdog runs continuously in timeout mode. the watchdog will be in timeout mode if wmc = 010 and the UJA1164 is in normal or standby mode. the wa tchdog will also be in timeout mode if wmc = 100 and the UJA1164 is in standby mode. if autonomous mode is selected (wmc = 001), the watchdog will be in timeout m ode if one of the conditions for timeout mode listed in ta b l e 1 0 has been satisfied. in timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. if the watchdog overflows, a watchdog failure event (wdf) is captured. if a wdf is already pending when the watchdog overflows, a syste m reset is performed. in timeout mode, the watchdog can be used as a cyclic wake-up source for the microcontroller when the UJA1164 is in standby mode. 6.2.4 watchdog behavior in autonomous mode autonomous mode is selected when wmc = 001. in autonomous mode, the watchdog is either off or in timeout mode, according to the conditions detailed in ta b l e 1 0 . table 10. watchdog status in autonomous mode UJA1164 operating mode watchdog status sdmc = 0 sdmc = 1 normal timeout mode off standby; rxd high off off any other mode off off standby; rxd low timeout mode off UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 13 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog when autonomous mode is selected, the watchdog will be in timeout mode if the sbc is in normal mode or standby mode with rxd low, provided software development mode has been disabled (sdmc = 0). otherwise the watchdog will be off. in autonomous mode, the watchdog will not be running when the sbc is in standby mode (rxd high). if a wake-up event is captured , pin rxd is forced low to signal the event and the watchdog is automatically restarted in timeout mode. 6.3 system reset when a system reset occurs, the sbc switch es to reset mode and initiates a process that generates a low-le vel pulse on pin rstn. 6.3.1 characteristics of pin rstn pin rstn is a bidirectional open drain low side driver with integrated pull-up resistance, as shown in figure 4 . with this configuration, the sbc can detect the pin being pulled down externally, e.g. by the microcon troller. a filter, with filter time t fltr(rst) , prevents a reset being triggered by noise etc. 6.3.2 selecting the reset pulse width the duration of the reset pulse is selected via bits rlc in the start-up control register ( ta b l e 11 ). the sbc distinguishes between a cold start and a warm start. a cold start is performed on start-up if the reset event was generated by a v1 undervoltage event. the reset pulse width for a cold start is determined by the setting of bits rlc. if the reset event was not triggered by a v1 undervoltage (e.g by a warm start of the microcontroller), the sbc always us es the shortest reset length (t w(rst) = 1 ms to 1.5 ms). fig 4. rstn internal pin configuration rstn v1 015aaa276 table 11. start-up control register (address 73h) bit symbol access value description 7:6 reserved r - 5:4 rlc r/w rstn reset pulse width: 00 [1] t w(rst) = 20 ms to 25 ms 01 t w(rst) = 10 ms to 12.5 ms 10 t w(rst) = 3.6 ms to 5 ms 11 t w(rst) = 1 ms to 1.5 ms 3:0 reserved r - UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 14 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] factory preset value. 6.3.3 reset sources the following events will cause the uja1 164 to switch to reset mode: ? v v1 drops below the selected v1 undervoltage threshold defined by bits v1rtc ? pin rstn is pulled down externally ? the watchdog overflows in window mode ? the watchdog is triggered too early in window mode (before t trig(wd)1 ) ? the watchdog overflows in timeout mode with wdf = 1 (watchdog failure pending) ? an attempt is made to reconf igure the watchdog control register while the sbc is in normal mode ? the sbc leaves off mode ? the sbc leaves overtemp mode 6.4 global temperature protection the temperature of the UJA1164 is monitored continuously, except in off mode. the sbc switches to overtemp mode if the temperat ure exceeds the overte mperature protection activation threshold, t th(act)otp . in addition, pin rstn is driven low and v1 and the can transceiver are switched off. when the temperature drops below the overtemperature protection release threshold, t th(rel)otp , the sbc switches to standby mode via reset mode. in addition, the UJA1164 provides an overte mperature warning. when the ic temperature rises about the overtemperature warning threshold (t th(warn)otp ), status bit otws is set and an overtemperature warning event is captured (otw = 1). 6.5 power supplies 6.5.1 battery supply voltage (v bat ) the internal circuitry is supplied from the battery via pin bat. the device needs to be protected against negative supply voltages, e. g. by using an external series diode. if v bat falls below the power-off detection threshold, v th(det)poff , the sbc switches to off mode. however, the microcontroller supply voltage (v1) remains active until v bat falls below 2 v. the sbc switches from off mode to reset mode t startup after the battery voltage rises above the power-on detection threshold, v th(det)pon . power-on event status bit po is set to 1 to indicate the UJA1164 has powered up and left off mode (see table 19 ). 6.5.2 low-drop voltage supply for 5 v microcontroller (v1) v1 is intended to supply the microcontroller and the internal can transceiver and delivers up to 150 ma at 5 v. the output voltage on v1 is monitored. a system reset is generated if the voltage on v1 drops below the selected undervoltage threshold (60 %, 70 %, 80 % or 90 % of the nominal v1 output voltage, se lected via v1rtc in the v1 control register; see ta b l e 1 2 ). UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 15 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog the internal can transceiver consumes 50 ma (max) when the bus is continuously dominant, leaving 100 ma available for the extern al load on pin v1. in practice, the typical current consumption of the can transceiver is lower ( ? 25 ma), depending on the application, leaving more current available for the load. the default value of the undervoltage threshold at power-up is determined by the value of bits v1rtsuc in the sbc configuration control register ( ta b l e 8 ). the sbc configuration control register is in non-vo latile memory, allowing the user to define the undervoltage threshold (v1rtc) at start-up. in addition, an undervoltage warning (a v1u event; see section 6.8 ) is generated if the voltage on v1 falls below 90 % of the nominal value (and v1u event det ection is enabled, v1ue = 1; see ta b l e 2 3 ). this information can be used as a warning, when the 60 %, 70 % or 80 % threshold is selected, to indicate that the level on v1 is outside the nominal supply range. the status of v1, whether it is above or below the 90 % undervoltage threshold, can be read via bit v1s in the supply voltage status register ( table 13 ). [1] default value at power-up defined by setting of bits v1rtsuc (see table 8 ). [1] default value at power-up. 6.6 high-speed can transceiver the integrated high-speed can transceiver is designed for bit rates up to 1 mbit/s, providing differential transmit and receive capability to a can protocol controller. the transceiver is iso 11898-2 and iso 11898-5 compliant. the can transmitter is supplied from v1. the can transceiver supports autonomous can biasing as defined in iso 11898-6, which helps to minimize rf emissions. canh and canl are always biased to 2.5 v when the transceiver is in active or listen-only modes (cmc = 01/10/11). autonomous biasing is active in can offline mo de - to 2.5 v if there is activity on the bus (can offline bias mode) and to gnd if th ere is no activity on the bus for t > t to(silence) (can offline mode). table 12. v1 control register (address 10h) bit symbol access value description 7:2 reserved r - 1:0 v1rtc [1] r/w set v1 reset threshold: 00 reset threshold set to 90 % of v1 nominal output voltage 01 reset threshold set to 80 % of v1 nominal output voltage 10 reset threshold set to 70 % of v1 nominal output voltage 11 reset threshold set to 60 % of v1 nominal output voltage table 13. supply voltage status register (address 1bh) bit symbol access value description 7:1 reserved r - 0 v1s r/w v1 status: 0 [1] v1 output voltage above 90 % undervoltage threshold 1 v1 output voltage below 90 % undervoltage threshold UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 16 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog this is useful when the node is disabled due to a malfunction in the microcontroller. the sbc ensures that the can bus is correctly biased to avoid disturbing ongoing communication between other nodes. the au tonomous can bias voltage is derived directly from v bat . 6.6.1 can operating modes the integrated can transceiver supports f our operating modes: active, listen-only, offline and offline bias (see figure 6 ). the can transceiver operating mode depends on the UJA1164 operating mode and on the settin g of bits cmc in the can control register ( ta b l e 1 4 ). when the UJA1164 is in normal mode, the can transceiver operating mode (active, listen-only or offline) can be selected via bits cmc in the can control register ( ta b l e 1 4 ). when the sbc is in standby mode, the tr ansceiver is forced to offline mode. 6.6.1.1 can active mode in can active mode, the transceiver can transmit and receive data via canh and canl. the differential receiver converts the analog data on the bus lines into digital data, which is output on pin rxd. the transmitter conv erts digital data generated by the can controller (input on pin txd) into analog signals suitable for transmission over the canh and canl bus lines. the can transceiver is in active mode when: ? the UJA1164 is in normal mode (mc = 111) and the can transceiver has been enabled by setting bits cmc in the can mode control register to 01 or 10 (see ta b l e 1 4 ) and the voltage on pin v1 is above the 90 % threshold or ? the UJA1164 is in forc ed normal mode with v v1 > 90 % of nominal value if pin txd is held low (e.g. by a short-circuit to gnd) when can active mode is selected via bits cmc, the transceiver will not enter can active mode but will switch to or remain in can listen-only mode. it will remain in listen -only mode until pin txd goes high in order to prevent a hardware and/or software application failure from driving the bus lines to an unwanted dominant state. in can active mode, the can bias voltage is derived from v1. if v1 falls below the 90 % threshold, the UJA1164 exits can active mo de and enters can offline bias mode with autonomous can voltage biasing via pin bat. if, however, the sbc is in forced normal mode when v1 falls below the 90 % thre shold, the transceiver switches to can listen-only mode to ensure as much as possible of the sbc remains active during the ecu development phase. the application can determine whether the can tr ansceiver is ready to transmit data or is disabled by reading the can transmitter status (cts) bit in the transceiver status register ( ta b l e 1 5 ). 6.6.1.2 can listen-only mode can listen-only mode allows the UJA1164 to mo nitor bus activity while the transceiver is inactive, without influencing bu s levels. this facility could be used by development tools that need to listen to the bus but do not need to transmit or receive data or for UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 17 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog software-driven selective wake-up. dedicated microcontrollers could be used for selective wake-up, providing an embedded low-power can engine designed to monitor the bus for potential wake-up events. in listen-only mode the can transmitter is disabled, reducing current consumption. the can receiver and can biasing remain active . this enables the host microcontroller to switch to a low-power mode in which an embedded can protocol controller remains active, waiting for a signal to wake up the microcontroller. the can transceiver is in listen-only mode when: ? the UJA1164 is in normal mode and cmc = 11 or ? the UJA1164 is in forced normal mode and v v1 < 90 % of nominal value or ? the UJA1164 is in normal mode, cmc = 01 or 10 and v v1 < 90 % of nominal value 6.6.1.3 can offline and offline bias modes in can offline mode, the transceiver monitors the can bus for a wake-up event, provided can wake-up detection is enabled (cwe = 1). canh and canl are biased to gnd. can offline bias mode is the same as can offline mode, with the exception that the can bus is biased to 2.5 v. this mode is activa ted automatically when activity is detected on the can bus while the transceiver is in can offline mode. the tran sceiver will return to can offline mode if the can bus is silent (no can bus edges) for longer than t to(silence) . the can transceiver will switch from can ac tive mode to can offline bias mode if: ? the sbc switches to reset or standby mode or ? the sbc is in normal mode and cmc = 00 or ? v v1 < 90 % of nominal value the can transceiver will switch from can listen-only mode to can offline bias mode if: ? the sbc switches to reset or standby mode or ? the sbc is in normal mode and cmc = 00 the can transceiver switches to can offline mode: ? from can offline bias mode if no activity is detected on the bus (no can edges) for t> t to(silence) or ? when the sbc switches from off or overtemp mode to reset mode the can transceiver switches from can off line mode to can offline bias mode if: ? a wake-up event is detected on the can bus or ? the sbc is in normal mode, cmc = 01 or 10 and v v1 <90 % 6.6.1.4 can off the can transceiver is switched off comple tely with the bus lines floating when: ? the sbc switches to of f or overtemp mode or ? v bat falls below the can receiver undervoltage detection threshold, v uvd(can) UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 18 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog it will be switched on again on ente ring can offline mode when v bat rises above the undervoltage release threshold and the sbc is no longer in off/overtemp mode. 6.6.2 can standard wake-up if the can transceiver is in offline mode and can wake-up is enabled (cwe = 1), the UJA1164 will monitor the bu s for a wake-up pattern. a filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or emi. a dominant-recessive-dominant wake-up pattern must be transmitted on the can bus within the wake-up timeout time (t to(wake) ) to pass the wake-up filter and trigger a wake-up event (see figure 5 ; note that additional pulses may occur between the recessive/dominant phases). the recessive and dominant phases must last at least t wake(busrec) and t wake(busdom) , respectively. when a valid can wake-up pattern is detected on the bus, wake-up bit cw in the transceiver event status register is set (see ta b l e 2 1 ) and pin rxd is driven low. fig 5. can wake-up timing t dom t wake(busdom) recessive t rec t wake(busrec) t dom t wake(busdom) dominant dominant 015aaa267 t wake < t to(wake) can wake-up UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 19 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog (1) to prevent the bus lines being driven to a permanent dominant stat e, the transceiver will not switch to can active mode if p in txd is held low (e.g. by a short-circuit to gnd) (2) when cmc = 01, a v1 undervoltage event (v v1 < 90 %) will cause the transceiver to exit active mode and the transmitter will be switched off. when cmc = 10, the transceiver will not immediately leave active mode in response to a v1 undervoltage event; the transmitter will remain active until the v1 reset threshold has been reached, when the sbc will switch to reset mode and the transceiver will switch to ca n offline or can offline bias mode. fig 6. can transceiver state machine & $ 1 $ f w l y h d d d w u d q v p l w w h u r i i u h f h l y h u r q 5 ; ' e l w v w u h d p & $ 1 + & $ 1 / w h u p l q d w h g w r 9 i u r p 9 % $ 7 & $ 1 / l v w h q r q o \ w u d q v p l w w h u r i i u h f h l y h u r i i 5 ; ' z d n h x s + , * + & $ 1 + & $ 1 / w h u p l q d w h g w r 9 i u r p 9 % $ 7 & $ 1 2 i i o l q h % l d v w u d q v p l w w h u r i i u h f h l y h u r i i 5 ; ' z d n h x s + , * + & $ 1 + & $ 1 / w h u p l q d w h g w r * 1 ' & $ 1 2 i i o l q h w ! w w r v l o h q f h > u h v h w 2 5 0 & 6 w d q g e \ 2 5 0 & 1 r u p d o & 0 & 2 i i o l q h @ w u d q v p l w w h u r i i u h f h l y h u r i i 5 ; ' z d n h x s + , * + & $ 1 + & $ 1 / i o r d w l q j & $ 1 2 i i o h d y l q j 2 i i 2 y h u w h p s 9 % $ 7 ! 9 x y u & $ 1 i u r p d o o p r g h v 2 i i 2 5 2 y h u w h p s 2 5 9 % $ 7 9 x y g & $ 1 w ! w w r v l o h q f h > u h v h w 2 5 0 & 6 w d q g e \ 2 5 0 & 1 r u p d o & 0 & 2 i i o l q h 2 5 9 9 @ w w w r v l o h q f h > u h v h w 2 5 0 & 6 w d q g e \ 2 5 0 & 1 r u p d o & 0 & 2 i i o l q h 2 5 9 9 @ 0 & 1 r u p d o & 0 & $ f w l y h 9 9 ! 0 & 1 r u p d o & 0 & / l v w h q r q o \ 2 5 ) 1 0 & 9 9 0 & 1 r u p d o & 0 & $ f w l y h 9 9 ! 2 5 ) 1 0 & 9 9 ! 0 & 1 r u p d o & 0 & / l v w h q r q o \ w w w r v l o h q f h > u h v h w 2 5 0 & 6 w d q g e \ 2 5 0 & 1 r u p d o & 0 & 2 i i o l q h @ w ! w w r v l o h q f h 0 & 1 r u p d o & 0 & $ f w l y h 9 9 ! 2 5 ) 1 0 & 9 9 ! z d n h x s 2 5 0 & 1 r u p d o & 0 & $ f w l y h 9 9 0 & 1 r u p d o & 0 & / l v w h q r q o \ 2 5 ) 1 0 & 9 9 0 & 1 r u p d o & 0 & $ f w l y h 9 9 w u d q v p l w w h u r q u h f h l y h u r q 5 ; ' e l w v w u h d p & $ 1 + & $ 1 / w h u p l q d w h g w r 9 9 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 20 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.6.3 can control and transceiver status registers [1] only active when cmc = 01. table 14. can control regi ster (address 20h) bit symbol access value description 7:2 reserved r/w - 1:0 cmc r/w can transceiver operating mode selection (available when UJA1164 is in normal mode; mc = 111): 00 offline mode 01 active mode (v cc undervoltage detection active for can state machine) 10 active mode (v cc undervoltage detection not active for can state machine) 11 listen-only mode table 15. transceiver status register (address 22h) bit symbol access value description 7 cts r 0 can transmitter disabled 1 can transmitter ready to transmit data 6:4 reserved r - 3 cbss r 0 can bus active (communication detected on bus) 1 can bus inactive (for longer than t to(silence) ) 2 reserved r - 1vcs [1] r 0 the output voltage on v1 is above the 90 % threshold 1 the output voltage on v1 is below the 90 % threshold 0 cfs r 0 no txd dominant timeout event detected 1 can transmitter disabled due to a txd dominant timeout event UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 21 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.7 can fail-safe features 6.7.1 txd dominant timeout a txd dominant time-out timer is starte d when pin txd is forced low while the transceiver is in can active mode. if the lo w state on pin txd persists for longer than the txd dominant time-out time (t to(dom)txd ), the transmitter is disabled, releasing the bus lines to recessive state. this function prev ents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). the txd dominant time-out timer is reset when pin txd goes high. the txd dominant time-out time also defines the minimum possible bit rate of 15 kbit/s. when the txd dominant time-out time is exceeded, a can failure event is captured (cf = 1; see ta b l e 2 1 ), if enabled (cfe = 1; see ta b l e 2 4 ). in addition, the status of the txd dominant timeout can be read via the cf s bit in the transceiver status register ( ta b l e 1 5 ) and bit cts is cleared. 6.7.2 pull-up on txd pin pin txd has an internal pull-up towards v1 to ensure a safe defined recessive driver state in case the pin is left floating. 6.7.3 v1 undervoltage event a can failure event is captured (cf = 1), if enabled, when the supply to the can transceiver (v1) falls below 90 % of its nominal value. in addition, status bit vcs is set to 1. 6.7.4 loss of power at pin bat a loss of power at pin bat has no influence on the bus lines or on the microcontroller. no reverse currents will flow from the bus. 6.8 wake-up and interrupt ev ent diagnosis via pin rxd wake-up and interrupt event diagnosis in the UJA1164 is intended to provide the microcontroller with information on the status of a range of features and functions. this information is stored in the event status registers ( ta b l e 1 9 to ta b l e 2 1 ) and is signaled on pin rxd, if enabled. a distinction is made between regular can wake-up events and interrupt events. table 16. regular events symbol event power-on description cw can wake-up disabled a can wake-up event was detected while the transceiver was in can offline mode. UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 22 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog po and wdf interrupts are always captured. wake-up and interrupt detection can be enabled/disabled for the remaining events individually via the event capture enable registers ( ta b l e 2 2 to ta b l e 2 4 ). if an event occurs while the associated event capture function is enabled, the relevant event status bit is set. if the transceiver is in can offline mode with v1 active (sbc normal or standby mode), pin rxd is forced low to indicate that a wake-up or interrupt event has been detected. the microcontroller can monitor events via t he event status register s. an extra status register, the global event status register ( table 18 ), is provided to help speed up software polling routines. by polling the gl obal event status register, th e microcontroller can quickly determine the type of event captured (system, supply or transceiver) and then query the relevant table ( ta b l e 1 9 , ta b l e 2 0 or table 21 respectively). after the event source has been identified, the relevant status bit should be cleared (set to 0) by writing 1 to th e relevant bit (writing 0 will have no effect). a number of status bits can be cleared in a single write operat ion by writing 1 to all relevant bits. it is strongly recommended to clear only the status bits that were set to 1 when the status registers were last read. this precaution ensures that events triggered just before the write access are not lost. 6.8.1 interrupt/wake-up delay if interrupt or wake-up events occur very freque ntly while the transceiv er is in can offline mode, they can have a significant impact on the software processing time (because pin rxd is repeatedly driven low, requiring a response from the microcontroller each time an interrupt/wake-up is generated). the UJA1164 incorporates an event delay timer to limit the disturbance to the software. table 17. diagnostic/interrupt events symbol event power-on description po power-on always enabled the UJA1164 has exited off mode (after battery power has been restored/connected) otw overtemperature warning disabled the ic temper ature has exceeded the overtemperature warning threshold spif spi failure disabled spi clock count error (o nly 16-, 24- and 32-bit commands are valid), illegal wmc, nwp or mc code or attempted write access to locked register wdf watchdog failure always enabled watchdog overflow in window or timeout mode or watchdog triggered too early in window mode; a system reset is triggered immediately in response to a watchdog failure in window mode; when the watchdog overflows in timeout mode, a system reset is only performed if a wdf is already pending (wdf = 1) v1u v1 undervoltage disabled voltage on v1 has dropped below the 90 % undervoltage threshold when v1 is active. v1u event capt ure is independent of the setting of bits v1rtc. cbs can bus silence disabled no activity on can bus for t to(silence) (detected only when cbse = 1 while bus active) cf can failure disabled one of the following can failure events detected: - can transceiver deactivated due to a v1 undervoltage - can transceiver deactivated due to a dominant clamped txd. UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 23 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog when one of the event capture status bits is cleared, pin rxd is released (high) and a timer is started. if further events occur while the timer is running, the relevant status bits are set. if one or more events are pending when the timer expires after t d(event) , pin rxd goes low again to alert the microcontroller. in this way, the microcontroller is interrupted once to process a number of events rather than several times to process individual events. if all events are cleared while the timer is running, rxd remains high after the timer expires, since there are no pending events. the event capture regi sters can be read at any time. the event capture delay timer is stopped i mmediately when pin rstn goes low (triggered by a high-to-low transition on the pin). rstn is driven low when the sbc enters reset, overtemp and off modes. 6.8.2 event status and event capture registers table 18. global event stat us register (address 60h) bit symbol access value description 7:3 reserved r - 2 trxe r 0 no pending transceiver event 1 transceiver event pending at address 0x63 1 supe r 0 no pending supply event 1 supply event pending at address 0x62 0 syse r 0 no pending system event 1 system event pending at address 0x61 table 19. system event status register (address 61h) bit symbol access value description 7:5 reserved r - 4 po r/w 0 no recent power-on 1 the UJA1164 has left off mode after power-on 3 reserved r - 2 otw r/w 0 overtemper ature not detected 1 the global chip temperature has exceeded the overtemperature warning threshold (t th(warn)otp ) 1 spif r/w 0 no spi failure detected 1 spi failure detected 0 wdf r/w 0 no watchdog failure event captured 1 watchdog failure event captured table 20. supply event status register (address 62h) bit symbol access value description 7:1 reserved r - 0 v1u r/w 0 no v1 undervoltage event captured 1 v1 undervoltage event captured UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 24 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog table 21. transceiver event status register (address 63h) bit symbol access value description 7:5 reserved r - 4 cbs r/w 0 can bus active 1 no activity on can bus for t to(silence) 3:2 reserved r - 1 cf r/w 0 no can failure detected 1 can transceiver deactivated due to v1 undervoltage or dominant clamped txd 0 cw r/w 0 no can wake-up event detected 1 can wake-up event detected while the transceiver is in can offline mode table 22. system event capture enable register (address 04h) bit symbol access value description 7:3 reserved r - 2 otwe r/w overtemperature warning event capture: 0 overtemperature warning disabled 1 overtemperature warning enabled 1 spife r/w spi failure detection: 0 spi failure detection disabled 1 spi failure detection enabled 0 reserved r - table 23. supply event capture enable register (address 1ch) bit symbol access value description 7:1 reserved r - 0 v1ue r/w v1 undervoltage detection: 0 v1 undervoltage detection disabled 1 v1 undervoltage detection enabled table 24. transceiver event capture enable register (address 23h) bit symbol access value description 7:5 reserved r - 4 cbse r/w can bus silence detection: 0 can bus silence detection disabled 1 can bus silence detection enabled 3:2 reserved r - 1 cfe r/w can failure detection 0 can failure detection disabled 1 can failure detection enabled 0 cwe r/w can wake-up detection: 0 can wake-up detection disabled 1 can wake-up detection enabled UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 25 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.9 non-volatile sbc configuration the UJA1164 contains multiple time progra mmable non-volatile (mtpnv) memory cells that allow some of th e default device settings to be reconfigured. the mtpnv memory address range is from 0x73 to 0x74. an overview of the mtpnv registers is given in ta b l e 2 5 . 6.9.1 programming mtpnv cells the UJA1164 must be in forced normal mode and the mtpnv cells must contain the factory preset values before the non-vol atile memory can be reprogrammed. the UJA1164 will switch to forced normal mode after a reset event (e.g. pin rstn low) when the mtpnv cells contain the fact ory preset values (since fnmc = 1). the factory presets may need to be restored before reprogramming can begin (see section 6.9.2 ). when the factory presets have been restored, a system reset is generated automatically and UJA1164 switches to fo rced normal mode. this ensures that the programming cycle cannot be interrupted by the watchdog. programming of the non-volatile memory register s is performed in two steps. firstly, the required values are written to addresse s 0x73 and 0x74. in the second step, reprogramming is confirmed by writing the correct crc value to the mtpnv crc control register (see section 6.9.1.1 ). the sbc starts reprogramming the mtpnv cells as soon as the crc value has been validated. if the cr c value is not correct, reprogramming is aborted. on completion, a system reset is generated to indicate that the mtpnv cells have been reprogrammed successfully. note that the mtpnv cells cannot be read while they are being reprogrammed. after an mtpnv programming cycle has been completed, the non-volatile memory is protected from being overwritten via a standard spi write operation. the mtpnv cells can be reprogrammed a maximum of 200 times (n cy(w)mtp ; see ta b l e 4 2 ). bit nvmps in the mtpnv status register ( ta b l e 2 6 ) indicates whether or not the non-volatile cells can be reprogramed. th is register also contains a write counter, wrcnts, that is incremented each time the mtpnv cells are reprogrammed (up to a maximum value of 111111; there is no overflow). note that this counter is provided for information purposes only; reprogramming will not be aborted if it reaches its maximum value. an error correction code status bit, eccs, indicates whether reprogramming was successful. table 25. overview of mtpnv registers address register name bit: 7 6 5 4 3 2 1 0 0x73 start-up control (see ta b l e 11 ) reserved rlc reserved 0x74 sbc configuration control (see ta b l e 8 ) reserved v1rtsuc fnmc sdmc reserved UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 26 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] factory preset value. 6.9.1.1 calculating the crc value for mtp programming the cyclic redundancy check value stored in bits crcc in the mtpnv crc control register is calculated using the data written to registers 0x73 and 0x74. the crc value is calculated using the data representation shown in figure 7 and the modulo-2 division with the generator polynomial: x 8 +x 5 + x 3 +x 2 + x + 1. the result of this operation must be bitwise inverted. the following parameters can be used to calculate the crc value (e.g. via the autosar method): table 26. mtpnv status register (address 70h) bit symbol access value description 7:2 wrcnts r xxxxxx write coun ter: contains the number of times the mtpnv cells were reprogrammed 1 eccs r 0 no error detected during mtpnv cell programming 1 an error was detected during mtpnv cell programming 0 nvmps r 0 mtpnv memory cannot be overwritten 1 [1] mtpnv memory is ready to be reprogrammed table 27. mtpnv crc control register (address 75h) bit symbol access value description 7:0 crcc r/w - crc control data fig 7. data representation for crc calculation table 28. parameters for crc coding parameter value crc result width 8 bits polynomial 0x2f initial value 0xff input data reflected no result data reflected no xor value 0xff 7 60 1 register 0x73 7 60 1 register 0x74 015aaa382 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 27 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog alternatively, the following algorithm can be used: data = 0 // unsigned byte crc = 0xff for i = 0 to 1 data = content_of_address(0x73 + i) exor crc for j = 0 to 7 if data ? 128 data = data * 2 // shift left by 1 data = data exor 0x2f else data = data * 2 // shift left by 1 next j crc = data next i crc = crc exor 0xff 6.9.2 restoring factory preset values factory preset values are restored if the following conditions apply for at least t d(mtpnv) during power-up: ? pin rstn is held low ? canh is pulled up to v bat ? canl is pulled down to gnd after the factory preset values have been restored, the sbc performs a system reset and enters forced normal mode. since the can bus is clamped dominant, pin rxdc is forced low. during the factory preset restore process, this pin is forced high; a falling edge on this pin caused by bit po being set after power-on then clearly indicates that the process has been completed. note that the write counter, wrcnts, in the mtpnv status register is incremented every time the factory presets are restored. 6.10 device id a byte is reserved at address 0x7e for a UJA1164 identification code. 6.11 lock control register sections of the register address area can be write-protected to protect against unintended modifications. note that this facility only protec ts locked bits from being modified via the spi and will not prevent the UJA1164 updating st atus registers etc. table 29. identification register (address 7eh) bit symbol access value description 7:0 ids[7:0] r 80h devic e identification code UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 28 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.12 general purpose memory UJA1164 allocates 4 bytes of ram as gene ral purpose registers for storing user information. the general purpose registers can be accessed via the spi at address 0x06 to 0x09 (see ta b l e 3 1 ). 6.13 spi 6.13.1 introduction the serial peripheral interface (spi) provides the communication link with the microcontroller, supporting multi-slave operat ions. the spi is configured for full duplex data transfer, so status information is returned when new control data is shifted in. the interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. the spi uses four interface signals for synchronization and data transfer: ? scsn: spi chip select; active low ? sck: spi clock; default level is low due to low-power concept (pull-down) ? sdi: spi data input table 30. lock control register (address 0ah) bit symbol access value description 7 reserved r - cleared for future use 6 lk6c r/w lock control 6: address area 0x68 to 0x6f 0 spi write-access enabled 1 spi write-access disabled 5 lk5c r/w lock control 5: address area 0x50 to 0x5f 0 spi write-access enabled 1 spi write-access disabled 4 lk4c r/w lock control 4: address area 0x40 to 0x4f 0 spi write-access enabled 1 spi write-access disabled 3 lk3c r/w lock control 3: address area 0x30 to 0x3f 0 spi write-access enabled 1 spi write-access disabled 2 lk2c r/w lock control 2: address area 0x20 to 0x2f - transceiver control 0 spi write-access enabled 1 spi write-access disabled 1 lk1c r/w lock control 1: address area 0x10 to 0x1f - regulator control 0 spi write-access enabled 1 spi write-access disabled 0 lk0c r/w lock control 0: address area 0x06 to 0x09 - general purpose memory 0 spi write-access enabled 1 spi write-access disabled UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 29 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog ? sdo: spi data output; floating when pin scsn is high bit sampling is performed on the falling edge of the cl ock and data is shifted in/out on the rising edge, as illustrated in figure 8 . the spi data in the UJA1164 is stored in a number of dedicated 8-bit registers. each register is assigned a unique 7-bit address. two bytes must be transmitted to the sbc for a single register write operation. the first byte contains the 7-bit address along with a ?read-only? bit (the lsb). the read-only bit must be 0 to indicate a write operation (if this bit is 1, a read operation is assumed and any data on the sdi pin is ignored). the second byte contains the data to be written to the register. 24- and 32-bit read and write operations are also supported. the register address is automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as illustrated in figure 9 . fig 8. spi timing protocol scsn sck 01 sampled floating floating 015aaa255 x x msb msbC1 msbC2 msbC3 01 lsb msb msbC1 msbC2 msbC3 01 lsb x sdi sdo 02 03 04 nC1 n UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 30 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog during an spi data read or write operation, the contents of the addr essed register(s) is returned via pin sdo. the UJA1164 tolerates attempts to write to registers that don?t exist. if the available address space is exceeded during a write operation, the data overflows into address 0x00. during a write operation, the UJA1164 monitors the number of spi bits transmitted. if the number recorded is not 16, 24 or 32, then the write operation is aborted and an spi failure event is captured (spif = 1). if more than 32 bits are clocked in on pin sd i during a read operation, the data stream on sdi is reflected on sd o from bit 33 onwards. fig 9. spi data structure for a writ e operation (16-, 24- or 32-bit) data byte 3 0x03 0x04 0x00 0x7f 0x01 0x05 0x07 0x02 0x06 0x7d 0x7e register address range xxxxxx x x data bits data id=0x05 data data address bits a5 a4 a3 a2 a1 a0 ro a6 xxxxxx x x data bits xxxxxx x x data bits addr 0000101 data byte 1 data byte 2 015aaa289 read-only bit UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 31 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.13.2 register map the addressable register space contains 128 registers with addresses from 0x00 to 0x7f. an overview of the register mapping is provided in ta b l e 3 1 to table 38 . the functionality of individual bits is discussed in more detail in relevant sections of the data sheet. table 31. overview of primary control registers address register name bit: 7 6 5 4 3 2 1 0 0x00 watchdog control wmc reserved nwp 0x01 mode control reserved mc 0x03 main status reserved otws nms rss 0x04 system event enable reserved otwe spife reserved 0x05 watchdog status reserved fnms sdms wds 0x06 memory 0 gpm[7:0] 0x07 memory 1 gpm[15:8] 0x08 memory 2 gpm[23:16] 0x09 memory 3 gpm[31:24] 0x0a lock control reserved lk6c lk5c lk4c lk3c lk2c lk1c lk0c table 32. overview of v1 and transceiver control registers address register name bit: 7 6 5 4 3 2 1 0 0x10 v1 control reserved v1rtc 0x1b supply status reserved v1s 0x1c supply event enable reserved v1ue 0x20 can control reserved cmc 0x22 transceiver status cts reserved cbss reserved vcs cfs 0x23 transceiver event enable reserved cbse reserved cfe cwe table 33. overview of event capture registers address register name bit: 7 6 5 4 3 2 1 0 0x60 global event status reserved trxe supe syse 0x61 system event status reserved po reserved otw spif wdf 0x62 supply event status reserved v1u 0x63 transceiver event status reserved cbs reserved cf cw table 34. overview of mtpnv status register address register name bit: 7 6 5 4 3 2 1 0 0x70 mtpnv status wrcnts eccs nvmps UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 32 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 6.13.3 register configuration in UJA1164 operating modes a number of register bits may change state automatically when the UJA1164 switches from one operating mode to another. this is particularly evident when the UJA1164 switches to off mode. these changes are summarized in table 39 . if an spi transmission is in progress when the UJA1164 changes stat e, the transmission is ignored (automatic state changes have priority). table 35. overview of startup control register address register name bit: 7 6 5 4 3 2 1 0 0x73 startup control reserved rlc reserved table 36. overview of sbc configuration control register address register name bit: 7 6 5 4 3 2 1 0 0x74 sbc configuration control reserved v1rtsuc fnmc sdmc reserved table 37. overview of crc control register address register name bit: 7 6 5 4 3 2 1 0 0x75 mtpnv crc control crcc[7:0] table 38. overview of identification register address register name bit: 7 6 5 4 3 2 1 0 0x7e identification ids[7:0] table 39. register bit settings in UJA1164 operating modes symbol off (power-on default) standby normal overtemp reset cbs 0 no change no change no change no change cbse 0 no change no change no change no change cbss 1 actual state actual stat e actual state actual state cf 0 no change no change no change no change cfe 0 no change no change no change no change cfs 0 actual state actual stat e actual state actual state cmc 00 no change no change no change no change crcc 00000000 no change no change no change no change cts 0 0 actual state 0 0 cw 0 no change no change no change no change cwe 0 no change no change no change no change eccs actual state actual state actual state actual state actual state fnmc mtpnv mtpnv mtpnv mtpnv mtpnv fnms 0 actual state actual stat e actual state actual state gpmn 00000000 no change no change no change no change UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 33 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] 001 if sdmc = 1; otherwise 010. ids 1000 0000 no change no change no change no change lknc 0 no change no change no change no change mc 100 100 111 don?t care 100 nms 1 no change 0 no change no change nvmps actual state actual state actual state actual state actual state nwp 0100 no change no change 0100 0100 otw 0 no change no change no change no change otwe 0 no change no change no change no change otws 0 actual state actual stat e actual state actual state po 1 no change no change no change no change rlc mtpnv mtpnv mtpnv mtpnv mtpnv rss 00000 no change no change 10010 reset source sdmc mtpnv mtpnv mtpnv mtpnv mtpnv sdms 0 actual state actual stat e actual state actual state spif 0 no change no change no change no change spife 0 no change no change no change no change supe 0 no change no change no change no change syse 1 no change no change no change no change trxe 0 no change no change no change no change v1rtc defined by v1rtsuc no change no change no change no change v1rtsuc mtpnv mtpnv mtpnv mtpnv mtpnv v1s 0 actual state actual stat e actual state actual state v1ue 0 no change no change no change no change v1u 0 no change no change no change no change vcs 0 actual state actual stat e actual state actual state wdf 0 no change no change no change no change wds 0 actual state actual stat e actual state actual state wmc [1] no change no change no change [1] wrcnts actual state actual state actual state actual state actual state table 39. register bit settings in UJA1164 operating modes ?continued symbol off (power-on default) standby normal overtemp reset UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 34 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 7. limiting values [1] when the device is not powered up, i v1 (max) = 25 ma. [2] verified by an external test house to ensure pins can withst and iso 7637 part 2 automotive transient test pulses 1, 2a, 3a a nd 3b. [3] esd performance according to iec 61000-4-2 (150 pf, 330 ? ) has been verified by an external test house; the result was equal to or better than ? 6 kv. [4] human body model (hbm): according to aec-q100-002 (100 pf, 1.5 k ? ). [5] v1 and bat connected to gnd, em ulating the application circuit. [6] machine model (mm): according to aec-q100-003 (200 pf, 0.75 ? h, 10 ? ). [7] charged device model (cdm): according to aec-q100-011 (field induced charge; 4 pf). [8] in accordance with iec 60747-1. an alternative def inition of virtual junction temperature is: t vj =t amb +p ? r th(j-a) , where r th(j-a) is a fixed value used in the calculation of t vj . the rating for t vj limits the allowable combinations of power dissipation (p) and ambient temperature (t amb ). table 40. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v x voltage on pin x dc value pin v1 [1] ? 0.2 +6 v pins txd, rxd, sdi, sdo, sck, scsn, rstn ? 0.2 v v1 +0.2 v pin bat ? 0.2 +40 v pins canh and canl with respect to any other pin ? 58 +58 v v (canh-canl) voltage between pin canh and pin canl ? 40 +40 v v trt transient voltage on pins bat: via reverse polarity diode and capacitor to ground canl, canh: coupling via 1 nf capacitors [2] ? 150 +100 v v esd electrostatic discharge voltage iec 61000-4-2 [3] on pins canh and canl; pin bat with capacitor ? 6+6 kv hbm [4] on pins canh, canl [5] ? 8+8 kv on pins bat ? 4+4 kv on any other pin ? 2+2 kv mm [6] on any pin ? 100 +100 v cdm [7] on corner pins ? 750 +750 v on any other pin ? 500 +500 v t vj virtual junction temperature [8] ? 40 +150 ?c t stg storage temperature ? 55 +150 ?c UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 35 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 8. thermal characteristics [1] according to jedec jesd51-2, jesd51-5 and jesd51-7 at natu ral convection on 2s2p board. board with two inner copper layers (thickness: 35 ? m) and thermal via array under the exposed pad connect ed to the first inner copper layer (thickness: 70 ? m). 9. static characteristics table 41. thermal characteristics symbol parameter conditions typ unit r th(vj-a) thermal resistance from virtual junction to ambient [1] 60 k/w table 42. static characteristics t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) =60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit supply; pin bat v th(det)pon power-on detection threshold voltage v bat rising 4.2 - 4.55 v v th(det)poff power-off detection threshold voltage v bat falling 2.8 - 3 v v uvr(can) can undervoltage recovery voltage v bat rising 4.5 - 5 v v uvd(can) can undervoltage detection voltage v bat falling 4.2 - 4.55 v i bat battery supply current standby mode; mc = 100; cwe = 1; can offline mode; i v1 = 0 ? a; v bat = 7 v to 18 v; ? 40 ? c < t vj <85 ?c -6085 ? a additional current in can offline bias mode; ? 40 ? c < t vj <85 ?c -4663 ? a normal mode; mc = 111; can active mode; can recessive; v txd =v v1 -47.5ma normal mode; mc = 111; can active mode; can dominant; v txd =0 v -4667ma voltage source: pin v1 v o output voltage v bat = 5.5 v to 18 v; i v1 = ? 120 ma to 0 ma; v txd =v v1 4.9 5 5.1 v v bat = 5.65 v to 18 v; i v1 = ? 150 ma to 0 ma; v txd =v v1 4.9 5 5.1 v v bat = 5.65 v to 18 v; i v1 = ? 100 ma to 0 ma; v txd =0 v; v canh = 0 v 4.9 5 5.1 v ? v ret(ram) ram retention voltage difference v bat = 2 v to 3 v; i v1 = ? 2 ma - - 100 mv v bat = 2 v to 3 v; i v1 = ? 200 ? a 10 mv UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 36 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog r (bat-v1) resistance between pin bat and pin v1 v bat = 4 v to 6 v; i v1 = ? 120 ma; t vj < 150 ?c --5 ? v bat = 3 v to 4 v; i v1 = ? 40 ma - 2.625 - ? v uvd undervoltage detection voltage v uvd(nom) = 90 % 4.5 - 4.75 v v uvd(nom) = 80 % 4 - 4.25 v v uvd(nom) =70% 3.5 3.75 v v uvd(nom) = 60 % 3 - 3.25 v v uvr undervoltage recovery voltage 4.5 - 4.75 v i o(sc) short-circuit output current ? 300 - ? 150 ma serial peripheral interface inputs; pins sdi, sck and scsn v th(sw) switching threshold voltage 0.25v v1 -0.75v v1 v r pd(sck) pull-down resistance on pin sck 40 60 80 k ? r pu(scsn) pull-up resistance on pin scsn 40 60 80 k ? i li(sdi) input leakage current on pin sdi ? 5-+5 ? a serial peripheral interface data output; pin sdo v oh high-level output voltage i oh = ? 4ma v v1 ? 0.4 - - v v ol low-level output voltage i ol = 4 ma - - 0.4 v i lo(off) off-state output leakage current v scsn = v v1 ; v o = 0 v to v v1 ? 5-+5 ? a can transmit data input; pin txd v th(sw) switching threshold voltage 0.25v v1 -0.75v v1 v r pu pull-up resistance 40 60 80 k ? can receive data output; pin rxd v oh high-level output voltage i oh = ? 4ma v v1 ? 0.4 - - v v ol low-level output voltage i ol = 4 ma - - 0.4 v r pu pull-up resistance can offline mode 40 60 80 k ? high-speed can bus lines; pins canh and canl v o(dom) dominant output voltage can active mode; v txd = 0 v pin canh 2.75 3.5 4.5 v pin canl 0.5 1.5 2.25 v v dom(tx)sym transmitter dominant voltage symmetry v dom(tx)sym = v v1 ? v canh ? v canl ; v v1 =5 v ? 400 - +400 mv v txsym transmitter voltage symmetry v txsym = v canh +v canl ; f txd = 250 khz; c split =4.7nf [1] [2] 0.9v v1 -1.1v v1 v v o(dif)bus bus differential output voltage can active mode (dominant); v txd = 0 v; v v1 = 4.75 v to 5.5 v; r (canh-canl) =45 ? to 65 ? 1.5 - 3.0 v can active mode (recessive); can listen-only mode; can offline mode; v txd = v v1 ; r (canh-canl) = no load ? 50 - +50 mv table 42. static characteristics ?continued t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) =60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 37 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog v o(rec) recessive output voltage can active mode; v txd = v v1 r (canh-canl) = no load 20.5v v1 3v can offline mode; r (canh-canl) = no load ? 0.1 - +0.1 v can offline bias/listen-only modes; r (canh-canl) = no load; v v1 = 0 v 22.53 v i o(dom) dominant output current can active mode; v txd =0v; v v1 =5 v pin canh; v canh =0v ? 50 - - ma pin canl; v canl =5v - - 52 ma i o(rec) recessive output current v canl = v canh = ? 27 v to +32 v; v txd = v v1 ? 3-+3 ma v th(rx)dif differential receiver threshold voltage can active/listen-only modes; v canl = v canh = ? 12 v to +12 v 0.5 0.7 0.9 v can offline mode; v canl = v canh = ? 12 v to +12 v 0.4 0.7 1.15 v v hys(rx)dif differential receiver hysteresis voltage can active/listen-only modes; v canl = v canh = ? 12 v to +12 v 50 200 400 mv r i(cm) common-mode input resistance 9 15 28 k ? ? r i input resistance deviation ? 1-+1 % r i(dif) differential input resistance v canl = v canh = ? 12 v to +12 v 19 30 52 k ? c i(cm) common-mode input capacitance [1] --20pf c i(dif) differential input capacitance [1] --10pf i li input leakage current v bat = v v1 =0v or v bat = v v1 = shorted to ground via 47 k ? ; v canh = v canl =5v ? 5-+5 ? a temperature protection t th(act)otp overtemperature protection activation threshold temperature 167 177 187 ?c t th(rel)otp overtemperature protection release threshold temperature 127 137 147 ?c t th(warn)otp overtemperature protection warning threshold temperature 127 137 147 ?c reset output; pin rstn v ol low-level output voltage v v1 = 1.0 v to 5.5 v; pull-up resistor to v v1 ? 900 ? 0 - 0.2v v1 v r pu pull-up resistance 40 60 80 k ? table 42. static characteristics ?continued t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) =60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 38 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] not tested in production; guaranteed by design. [2] the test circuit used to measure the bus output voltage symmetry (which includes c split ) is shown in figure 14 . v th(sw) switching threshold voltage 0.25 v1 -0.75v v1 v mtp non-volatile memory n cy(w)mtp number of mtp write cycles - - 200 - table 42. static characteristics ?continued t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) =60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 39 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 10. dynamic characteristics table 43. dynamic characteristics t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) = 60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit voltage source; pin v1 t startup start-up time from v bat exceeding the power-on detection threshold until v v1 exceeds the 90 % undervoltage threshold -2.84.7ms t d(uvd) undervoltage detection delay time 6 - 39 ? s t d(uvd-rstnl) delay time from undervoltage detection to rstn low undervoltage on v1 - - 48 ? s t d(buswake-voh) delay time from bus wake-up to high-level output voltage high = 0.8v o(v1) ; i v1 ? 100 ma --5ms serial peripheral interface timing; pins scsn, sck, sdi and sdo t cy(clk) clock cycle time 250 - - ns t spilead spi enable lead time 50 - - ns t spilag spi enable lag time 50 - - ns t clk(h) clock high time 125 - - ns t clk(l) clock low time 125 - - ns t su(d) data input set-up time 50 - - ns t h(d) data input hold time 50 - - ns t v(q) data output valid time pin sdo; c l = 20 pf - - 50 ns t wh(s) chip select pulse width high pin scsn 250 - - ns can transceiver timi ng; pins canh, canl, txd and rxd t d(txd-rxd) delay time from txd to rxd 50 % v txd to 50 % v rxd ; c rxd = 15 pf; f txd = 250 khz --255ns t d(txd-busdom) delay time from txd to bus dominant -80-ns t d(txd-busrec) delay time from txd to bus recessive -80-ns t d(busdom-rxd) delay time from bus dominant to rxd c rxd = 15 pf - 105 - ns t d(busrec-rxd) delay time from bus recessive to rxd c rxd = 15 pf - 120 - ns t wake(busdom) bus dominant wake-up time first pulse (after first recessive) for wake-up on pins canh and canl; can offline mode 0.5 - 3.0 ? s second pulse for wake-up on pins canh and canl 0.5 - 3.0 ? s UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 40 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog [1] a system reset will be performed if the watchdog is in window mode and is triggered less than t trig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). [2] the nominal watchdog period is programmed via the nwp control bits. [3] the watchdog will be reset if it is in window mode and is triggered at least t trig(wd)1 , but not more than t trig(wd)2 , after the start of the watchdog period (or in the second half of the watchdog period). a system reset will be performed if the watchdog is triggered m ore than t trig(wd)2 after the start of the watchdog period (watchdog overflows). t wake(busrec) bus recessive wake-up time first pulse for wake-up on pins canh and canl; can offline mode 0.5 - 3.0 ? s second pulse (after first dominant) for wake-up on pins canh and canl 0.5 - 3.0 ? s t to(wake) wake-up time-out time between first and second dominant pulses; can offline mode 570 - 1200 ? s t to(dom)txd txd dominant time-out time can active mode; v txd = 0 v 2.7 - 3.3 ms t to(silence) bus silence time-out time recessive time measurement started in all can modes; r l = 120 ? 0.95 - 1.17 s t d(busact-bias) delay time from bus active to bias - - 200 ? s t startup(can) can start-up time when switching to active mode (cts = 1) --220 ? s pin rxd: event capture timing (v alid in can offline mode only) t d(event) event capture delay time can offline mode 0.9 - 1.1 ms t blank blanking time when switching from offline to active/listen-only mode --25 ? s watchdog t trig(wd)1 watchdog trigger time 1 normal mode; watchdog window mode only [1] 0.45 ? nwp [2] -0.55 ? nwp [2] ms t trig(wd)2 watchdog trigger time 2 normal/standby mode [3] 0.9 ? nwp [2] -1.11 ? nwp [2] ms pin rstn: reset pulse width t w(rst) reset pulse width rlc = 00 20 - 25 ms rlc = 01 10 - 12.5 ms rlc = 10 3.6 - 5 ms rlc = 11 1 - 1.5 ms t fltr(rst) reset filter time 7 - 18 ? s mtp non-volatile memory t d(mtpnv) mtpnv delay time before factory presets are restored 0.9 - 1.1 ms table 43. dynamic characteristics ?continued t vj = ? 40 ? c to +150 ? c; v bat = 3 v to 28 v; r (canh-canl) = 60 ? ; all voltages are defined with respect to ground; positive currents flow into the ic; ty pical values are given at v bat = 13 v; unless otherwise specified. symbol parameter conditions min typ max unit UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 41 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog fig 10. can transceiver timing diagram & $ 1 + & $ 1 / w g 7 ; ' e x v g r p 7 ; ' 9 2 g l i e x v 5 ; ' + , * + + , * + / 2 : / 2 : g r p l q d q w u h f h v v l y h 9 9 w g e x v g r p 5 ; ' w g 7 ; ' e x v u h f w g e x v u h f 5 ; ' w g 7 ; ' 5 ; ' w g 7 ; ' 5 ; ' d d d fig 11. spi timing diagram d d d 6 & 6 1 6 & . 6 ' , 6 ' 2 ; ; ; 0 6 % / 6 % 0 6 % / 6 % w y 4 i o r d w l q j i o r d w l q j w k ' w v x ' w f o n / w f o n + w 6 3 , / ( $ ' w f \ f o n w 6 3 , / $ * w : + 6 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 42 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 11. application information 11.1 application diagram (1) actual capacitance value must be a least 1.76 ? f with 5 v dc offset (recommended capacitor value is 4.7 ? f) (2) for bus line end nodes, r t = 60 ? in order to support the ?split terminat ion concept?. for sub- nodes, an optional ?weak? termination of e.g. r t = 1.3 k ? can be used, if required by the oem. fig 12. typical application using the UJA1164 sdo 015aaa381 rstn UJA1164 3 gnd 5 rstn micro- controller 6 8 sck rxd rxd 4 txd txd 1 sdi 11 14 scsn standard c ports v cc v 1 12 13 2 bat 10 bat v ss 22 f (1) canh canl e.g. 4.7 nf r t (2) r t (2) UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 43 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 12. test information 12.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. fig 13. timing test circuit for can transceiver fig 14. test circuit for measuring transceiver driver symmetry sbc bat canl canh txd r l rxd 15 pf gnd 100 pf 015aaa369 015aaa444 canh 13 10 12 canl sbc 4.7 nf 30 30 txd rxd gnd 1 4 bat 2 f = 250 khz c split UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 44 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 13. package outline fig 15. package outline sot1086-2 (hvson14) references outline version european projection issue date iec jedec jeita sot1086-2 - - - mo-229 - - - sot1086-2 10-07-14 10-07-15 unit mm max nom min 1.00 0.85 0.80 0.05 0.03 0.00 0.2 4.6 4.5 4.4 4.25 4.20 4.15 3.1 3.0 2.9 0.65 3.9 0.45 0.40 0.35 0.1 a dimensions hvson14: plastic, thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 x 4.5 x 0.85 mm sot1086-2 a 1 b 0.35 0.32 0.29 cdd h ee h 1.65 1.60 1.55 ee 1 k 0.35 0.30 0.25 lv 0.1 w 0.05 y 0.05 y 1 0 2.5 5 mm scale b a terminal 1 index area d e x detail x a c a 1 c y c y 1 ac b v c w b terminal 1 index area e 1 e d h e h l k 1 14 7 8 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 45 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 14. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are: UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 46 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 15.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 16 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 4 and 45 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 16 . table 44. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 45. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 47 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 16. soldering of hvson packages section 15 contains a brief introduction to the te chniques most commonly used to solder surface mounted devices (smd). a more detailed discussion on soldering hvson leadless package ics can found in the following application notes: ? an10365 ?surface mount reflow soldering description? ? an10366 ?hvqfn application information? msl: moisture sensitivity level fig 16. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 48 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 17. revision history table 46. revision history document id release date data sheet status change notice supersedes UJA1164 v.1 20130805 product data sheet - - UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 49 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 50 of 52 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com UJA1164 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 august 2013 51 of 52 continued >> nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 designed for automotive applications. . . . . . . . 1 2.3 low-drop voltage regulator for 5 v microcontroller supply (v1) . . . . . . . . . . . . . . . . 1 2.4 power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 system control and diagnostic features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 system controller . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.2 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.3 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.1.4 off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.1.5 overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.1.6 forced normal mode . . . . . . . . . . . . . . . . . . . . 7 6.1.1.7 hardware characterization for the UJA1164 operating modes . . . . . . . . . . 8 6.1.2 system control registers . . . . . . . . . . . . . . . . . . 8 6.2 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.1 software development mode . . . . . . . . . . . . . 12 6.2.2 watchdog behavior in window mode . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.3 watchdog behavior in timeout mode . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.4 watchdog behavior in autonomous mode . . . . . . . . . . . . . . . . . . . 12 6.3 system reset. . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3.1 characteristics of pin rstn . . . . . . . . . . . . . . 13 6.3.2 selecting the reset pulse width . . . . . . . . . . . . 13 6.3.3 reset sources. . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 global temperature protection . . . . . . . . . . . . 14 6.5 power supplies . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5.1 battery supply voltage (v bat ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5.2 low-drop voltage supply for 5 v microcontroller (v1) . . . . . . . . . . . . . . . . . . . . 14 6.6 high-speed can transceiver . . . . . . . . . . . . . 15 6.6.1 can operating modes . . . . . . . . . . . . . . . . . . 16 6.6.1.1 can active mode . . . . . . . . . . . . . . . . . . . . . . 16 6.6.1.2 can listen-only mode . . . . . . . . . . . . . . . . . . 16 6.6.1.3 can offline and offline bias modes . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6.1.4 can off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6.2 can standard wake-up . . . . . . . . . . . . . . . . . 18 6.6.3 can control and transceiver status registers . . . . . . . . . . . . . . 20 6.7 can fail-safe features . . . . . . . . . . . . . . . . . . 21 6.7.1 txd dominant timeout . . . . . . . . . . . . . . . . . . 21 6.7.2 pull-up on txd pin. . . . . . . . . . . . . . . . . . . . . 21 6.7.3 v1 undervoltage event . . . . . . . . . . . . . . . . . . 21 6.7.4 loss of power at pin bat . . . . . . . . . . . . . . . . 21 6.8 wake-up and interrupt event diagnosis via pin rxd . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8.1 interrupt/wake-up delay . . . . . . . . . . . . . . . . . 22 6.8.2 event status and event capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.9 non-volatile sbc configuration . . . . . . . . . . . 25 6.9.1 programming mtpnv cells . . . . . . . . . . . . . . 25 6.9.1.1 calculating the crc value for mtp programming . . . . . . . . . . . . . . . . . . 26 6.9.2 restoring factory preset values . . . . . . . . . . . 27 6.10 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.11 lock control register. . . . . . . . . . . . . . . . . . . . 27 6.12 general purpose memory . . . . . . . . . . . . . . . 28 6.13 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.13.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.13.3 register configuration in UJA1164 operating modes . . . . . . . . . . . . . 32 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34 8 thermal characteristics . . . . . . . . . . . . . . . . . 35 9 static characteristics . . . . . . . . . . . . . . . . . . . 35 10 dynamic characteristics. . . . . . . . . . . . . . . . . 39 11 application information . . . . . . . . . . . . . . . . . 42 11.1 application diagram . . . . . . . . . . . . . . . . . . . . 42 12 test information . . . . . . . . . . . . . . . . . . . . . . . 43 12.1 quality information . . . . . . . . . . . . . . . . . . . . . 43 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 44 14 handling information . . . . . . . . . . . . . . . . . . . 45 15 soldering of smd packages . . . . . . . . . . . . . . 45 15.1 introduction to soldering. . . . . . . . . . . . . . . . . 45 15.2 wave and reflow soldering. . . . . . . . . . . . . . . 45 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 45 15.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 46 16 soldering of hvson packages . . . . . . . . . . . 47 nxp semiconductors UJA1164 mini high-speed can s ystem basis chip wi th standby mode & watchdog ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 5 august 2013 document identifier: UJA1164 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 48 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 49 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 49 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 19 contact information. . . . . . . . . . . . . . . . . . . . . 50 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 |
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